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CFD Runtime Acceleration on New Chip Architecture

TECHNOLOGY AREA(S): Information Systems OBJECTIVE: Develop a callable library of CFD numerical operations that exploit the performance of CFD solvers on new ?many integrated core? processors such as the Intel? Xeon PhiTM. DESCRIPTION: Computer chip makers like Intel have recently introduced the advanced Many-Integrated-Core (MIC) architecture [1] with the goal of enhancing performance for numerically intensive calculations like satellite imaging and computer gaming. These new processors offer an enormous increase in speed for these types of calculations over the more traditional chips that support standard PC applications. Recently, the DoD has began to upgrade their parallel High Performance Computer (HPC) systems to use these MIC processors because they greatly enhance the degree of parallelism available for numerical operations. Computational Fluid Dynaimic (CFD) codes used in Army rotorcraft analysis [2] could greatly benefit from these performance enhancements. Typical CFD runs today that require a week of compute time could be reduced to a day, making routine design iterations possible. Exploiting this enhanced degree of parallelism requires new programming strategies to exploit the vector processing units (VPUs) of the MIC architecture. Traditional MPI-based programming strategies used in the CFD codes today will not be effective [3]. CFD Codes are being developed in house and will be provided.This proposal solicits a library of numerical operations performed by our CFD codes that achieve optimal performance on the MIC architectures. The Army’s CFD codes are memory-bound, and the many-way parallelism offered by the MIC architecture will not increase the degree of memory available on today?s processors. Hence, the proposed library should additionally include an analysis of the amount of memory used by the application. Specific requirements for the library include: ? Numerical operations that achieve optimal performance on MIC architectures? Runtime memory analysis to determine when the problem size is too large? Ability to be compiled with Army CFD codes under different compilers? Cross platform compatibility (i.e. not specific to any particular operating system). PHASE I: Demonstrate a callable library of a small subset of numerical operations in Army CFD codes that run on MIC processors. PHASE II: Expand the library to include the wider set of numerical operations encompassing the entire CFD code. Demonstrate performance gains over traditional programming paradigms. Demonstrate memory reporting and clean shutdown when memory limits are exceeded. Demonstrate application of the library and performance gains for to real-world rotorcraft CFD calculations. PHASE III DUAL USE APPLICATIONS: Operations in the library may be extended to include computational structural dynamics (CSD), comprehensive analysis, and other scientific computing applications of interest to the Army. COMMERCIALIZATION: The proposed library can be readily used by commercial CFD codes developed outside the Army. KEYWORDS: High Performance Computing, Intel MIC, parallel computing POINT OF CONTACT: Andrew Wissink, Phone: 650-604-5385, Email: andrew.m.wissink@us.army.mil

  • Agency: Army,Department of Defense,Department of Defense
  • Program: SBIR
  • Phase: Phase I
  • Release Date: August 27, 2015
  • Open Date: September 28, 2015
  • Close Date: October 28, 2015
  • URL: https://sbir.defensebusiness.org/topics
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