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Analog Co-Processors for Complex System Simulation and Design

TECHNOLOGY AREA(S): Information Systems, Materials/Processes OBJECTIVE: Demonstrate that, in certain critical applications, analog processing architectures can significantly outperform the equivalent digital architectures and motivate the larger development and use of analog methods DARPA broadly in defense systems. DESCRIPTION: The efficient simulation of complex systems is of fundamental importance to the Department of Defense (DoD), the scientific community, and the commercial sector. However, today?s digital computational architectures are in many cases ill-suited to the mathematical models that power these simulations. Recent research suggests that analog processors could be used in hybrid continuous-digital systems to accelerate computational problems that are intractable with current discrete variable encoding and serial processing.The general purpose computer, conceived in the 1930?s by Turing, was at first too large and slow to be practical in most applications. As late as the 1960?s a mainstay of computation, particularly for controls and signal processing, was analog processing, first mechanical and then electrical. But by the 1970?s the development of the digital integrated circuit, high capacity memory, and high level programming languages pushed analog computing into the background.Nevertheless, because of analog computation?s repertoire of rich primitives and its inherent parallel architecture, analog computation can still be far faster, more efficient, and more compact than digital computation for many applications. For example, an 8-bit multiplication of two currents in analog computation takes 4 to 8 transistors, whereas a parallel 8-bit multiply in digital computation takes approximately 3000 transistors. Furthermore, recent advances in op-amp performance (several Ghz) and re-configurability (introduction of the field programmable analog array) could commend analog processing for applications requiring high performance but constrained by low size, weight, and power.Analog systems may have other important advantages over digital systems. First, as a natural solver of partial differential equations, the analog computer can be a much closer proxy to the actual physical processes that it is used to compute. This should mean that it is more effective at modeling ?stiff? systems of equations (incompressible fluid flow, for instance) and should be much less affected by discretization errors. In addition, analog processing is immune to single event upsets, and may be less vulnerable to tampering.This STTR seeks innovative approaches to demonstrate in actual hardware the ability of analog or hybrid-analog computation to outperform digital architecture employed in current applications. Such applications may include image processing, mathematical simulation of complex systems, parametric design exploration and optimization, etc. The demonstration may be as a standalone processor or as a coprocessor in a digital system and must be relevant to a national security problem. PHASE I: Develop an analog architecture for efficient computation of partial differential equations. Identify the computational substrate and the physical dynamics of the structure that will encode or instantiate the analog representation. Describe how the analog processes will perform computation, and how the results will be measured. Define a target problem class informed by current computational and analytic limitations. Estimate the relative theoretical speedup versus best-in-class numerical or analytic alternatives, how the method scales to problem size/dimensionality, and any restrictions on the generalizability of the approach. Phase I deliverable is a final report documenting effort and results. PHASE II: Demonstrate the key technical principles behind the proposed computational substrate. The demonstration should validate the predicted superior performance of the analog approach over a comparable digital approach and show the relevance of the demonstration to at least three real-world applications. The required deliverables for the end of Phase II include a prototype implementation of the techniques defined in Phase I and a final report that includes the demonstration system design and test results. PHASE III DUAL USE APPLICATIONS: A successful Phase II demonstration will motivate a number of applications and insertions into commercial systems (natural language understanding, transportation optimization, power management, etc.).A successful Phase II demonstration will enable a number of applications and insertions into defense systems (onDARPA board processing, space systems, automatic target recognition, etc.). KEYWORDS: analog, digital, array, massively parallel, optimization, signal processing  POINT OF CONTACT: Dr. Vincent Tang, Phone: 703-527-2845, Email: vincent.tang@darpa.mil

  • Agency: Defense Advanced Research Projects Agency,Department of Defense,Department of Defense
  • Program: STTR
  • Phase: Phase I
  • Release Date: August 27, 2015
  • Open Date: September 28, 2015
  • Close Date: October 28, 2015
  • URL: https://sbir.defensebusiness.org/topics
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